Professor Joseph Bernstein is an expert in several areas of nano-scale micro-electronic device reliability and physics of failure; including packaging, system reliability modeling, gate oxide integrity, radiation effects, Flash NAND and NOR memory, SRAM and DRAM, MEMS and laser programmable metal interconnect.  He has licensed his own technology and consulted for RFID and SRAM applications related to fuse and redundancy and for programmable gate arrays and system-on-chip.

He directs the Laboratory for Failure Analysis and Reliability of Electronic Systems, teaches VLSI design courses and heads the VLSI program at Ariel University. His Laboratory is a center of research activity dedicated to serving the needs of manufacturers of highly reliable electronic systems using commercially available off the shelf parts. His latest project is to qualify COTS for satellite operation and works with the FIDES European reliability standards. His formulations have become integrated throughout much of the electronics industry. He lectures around the world, presenting his common-sense approach to reliability testing and reliability. He also closely works with both testing and reliability software companies.